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Diffstat (limited to 'www')
| -rw-r--r-- | www/design.html | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/www/design.html b/www/design.html index 0fe2b1a2..5380bd74 100644 --- a/www/design.html +++ b/www/design.html @@ -55,7 +55,7 @@ plus this cacheing</a>, and this one on <a href=http://arstechnica.com/articles/paedia/cpu/bandwidth-latency.ars>bandwidth and latency</a>. -And there's <a href=http://arstechnica.com/paedia/>more where that came from</a>.) +And there's <a href=http://arstechnica.com/paedia/index.html>more where that came from</a>.) Running out of L1 cache can execute one instruction per clock cycle, going to L2 cache costs a dozen or so clock cycles, and waiting for a worst case dram fetch (round trip latency with a bank switch) can cost thousands of |