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authorRob Landley <rob@landley.net>2007-05-17 02:38:17 -0400
committerRob Landley <rob@landley.net>2007-05-17 02:38:17 -0400
commit8e0520c3ac41b37ccd8937ce3a81f9ab04e2a189 (patch)
tree3c1e6b7cfaf36def9ba748854821e9df58f0816c
parentf2ccc2d1d6f58d8f6162f2596bcbba7e275df53c (diff)
downloadtoybox-8e0520c3ac41b37ccd8937ce3a81f9ab04e2a189.tar.gz
Link to ars technica paedia broke because ars is now using Windows 2003 on
its' webserver and can't competently show "index.html" for a directory. Wheee.
-rw-r--r--www/design.html2
1 files changed, 1 insertions, 1 deletions
diff --git a/www/design.html b/www/design.html
index 0fe2b1a2..5380bd74 100644
--- a/www/design.html
+++ b/www/design.html
@@ -55,7 +55,7 @@ plus this
cacheing</a>, and this one on
<a href=http://arstechnica.com/articles/paedia/cpu/bandwidth-latency.ars>bandwidth
and latency</a>.
-And there's <a href=http://arstechnica.com/paedia/>more where that came from</a>.)
+And there's <a href=http://arstechnica.com/paedia/index.html>more where that came from</a>.)
Running out of L1 cache can execute one instruction per clock cycle, going
to L2 cache costs a dozen or so clock cycles, and waiting for a worst case dram
fetch (round trip latency with a bank switch) can cost thousands of